In information processing systems, memory sub-system testing for synchronous DRAM (SDRAM) is not easily achieved unless the memory controller is specifically designed to achieve that task. SDRAM data typically flows directly to the microprocessor in the case of high performance systems. Since the Error Correction Code (ECC) block is generally between a microprocessor bus and the SDRAM data, specially designed ECC blocks are required to force errors in the "read" path, or to read the ECC check bits that have been generated.
Thus, ECC techniques have involved the application of special processing and programming by a memory controller and the introduction of special hardware into a processing system solely for the purpose of testing selected sections of the system. In the past, ECC has operated by dedicated data paths to memory that bypass the ECC data paths, or special circuitry to simulate errors on reading a memory word. Typically, such testing circuitry has been quite complex and extensive and still falls short of providing optimum testability and returned results for memory subsystems with regard to the identification and specification of malfunctions, especially in memory testing.
Accordingly, there is a need for an improved testing apparatus and methodology which is effective to provide more accurate testing results and identification of faults within a memory subsystem being tested.